A LOW-POWER ANALOG SAMPLED-DATA VLSI ARCHITECTURE FOR EQUALIZATION AND FDTS/DF DETECTION

The design philosophy behind a low-power integrated circuit architecture for implementing an FDTS/DF magnetic recording channel is presented. The goal of this philosophy is to achieve high clock speed, moderate power consumption, and relatively small die area. The principle components that are considered are a programmable FIR sampled-data analog equalizer and an analog sampled-data FDTS/DF detector. These blocks are implemented using sampled-data analog signal processing circuitry to avoid the need for a high-speed high-power analog-to-digital converter. Novel features of the FIR equalizer architecture include sampling of current rather than voltage, which allows extremely high sampling bandwidth; and, analog multiplication using MOS devices in their linear region which achieves a power dissipation on the order of 5mW/tap at 100MS/s.