SEU SIMULATION AND TESTING OF RESISTOR-HARDENED D-LATCHES IN THE SA3300-MICROPROCESSOR

The SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm2/mg with no feedback resistors to 60 MeV-cm2/mg and 180 MeV-cm2/mg with feedback resistors of 50 k-OMEGA and 160 k-OMEGA, respectively. The performance goal of 10 MHz over the full temperature range of -55-degrees-C to +125-degrees-C is exceeded for feedback resistors of 160 k-OMEGA and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 k-OMEGA feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5-mu-m. This is much deeper than we would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate.