A NEW SYSTOLIC DESIGN FOR DIGITAL IIR FILTERS

被引：5

作者：

JAYADEVA

机构：

[1] Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS | 1990年 / 37卷 / 05期

关键词：

D O I：

10.1109/31.55012

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two systolic implementations of digital IIR filters have been presented and compared with the designs of Luk and Jones [1]. It is shown that they represent a general class of systolic filters which reduce to canonical delay implementations in the limit. © 1990 IEEE

引用

页码：653 / 654

页数：2