VARIABILITY REDUCTION IN CMOS OPERATIONAL-AMPLIFIERS THROUGH LAYOUT MODIFICATION

被引：1

作者：

BHATTACHARYYA, AB ^{[1
]}

AGGARWAL, S ^{[1
]}

机构：

[1] UNIV ROCHESTER, DEPT ELECT ENGN, ROCHESTER, NY 14627 USA

来源：

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS | 1989年 / 136卷 / 02期

关键词：

D O I：

10.1049/ip-g-2.1989.0012

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：79 / 83

页数：5

共 10 条

[1]

[Anonymous], QUALITY CONTROL IND

[2]

BRAYTON RK, 1980, SENSITIVITY OPTIMIZA

[3] VARIABILITY ANALYSIS AND DESIGN OF AN INTEGRATED-CIRCUIT USING SENSITIVITY INFORMATION [J].

HAASAKKER, B ;

JONES, IW .

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1982, 129 (04) :192-198

[4] COST REDUCTION OF MONTE-CARLO YIELD ESTIMATES [J].

JONES, IW ;

SPENCE, R .

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1987, 134 (06) :249-258

[5] CHARACTERIZATION AND MODELING OF MISMATCH IN MOS-TRANSISTORS FOR PRECISION ANALOG DESIGN [J].

LAKSHMIKUMAR, KR ;

HADAWAY, RA ;

COPELAND, MA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (06) :1057-1066

[6] STATISTICAL MODELING FOR INTEGRATED-CIRCUITS [J].

RANKIN, PJ .

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1982, 129 (04) :186-191

[7]

SOBCZAC A, 1981, AUG P EUR C CIRC THE, P587

[8] A PROCESS-INSENSITIVE HIGH-PERFORMANCE NMOS OPERATIONAL-AMPLIFIER [J].

TSIVIDIS, YP ;

FRASER, DL ;

DZIAK, JE .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (06) :921-928

[9] INTEGRATED NMOS OPERATIONAL-AMPLIFIER WITH INTERNAL COMPENSATION [J].

TSIVIDIS, YP ;

GRAY, PR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (06) :748-753

[10] HIGH-PERFORMANCE ALL-ENHANCEMENT NMOS OPERATIONAL-AMPLIFIER [J].

YOUNG, IA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (06) :1070-1077

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