MINIMIZING THE NUMBER OF DELAY BUFFERS IN THE SYNCHRONIZATION OF PIPELINED SYSTEMS

When designing a pipelined digital system, delay buffers (often implemented as shift registers) are usually introduced into the system in order to synchronize the various signals impinging on each and every processing element. By thus insuring that all related inputs to each processing element arrive at precisely the same time, additional memory for this purpose need not be included within the processing elements themselves. The design of these elements may therefore be carried out independently of the topologies of the systems within which they will ultimately appear. Clearly, any solution to this synchronization problem is not likely to be unique; that is, there will usually exist many combinations of buffer locations and lengths that can produce overall input data synchronization in a typical pipelined network. When selecting one solution from many available solutions, it is natural to observe that it would be beneficial to implement a solution that makes use of the minimum number of total delay buffer stages necessary to produce synchronization in order that the system hardware cost and complexity may be reduced. In this paper, we present a technique to solve this delay buffer problem in polynomial time. Unlike other polynomial-time methods, this approach solves both the pipeline synchronization and buffer minimization problems within a single formulation. Furthermore, this technique is readily extended to handle pipelined systems containing feedback loops as well as processing elements whose fanout loads are greater than one. It has been used in a synthesis design environment described in [1].