ENHANCEMENT OF FLIP-CHIP FATIGUE LIFE BY ENCAPSULATION

被引:73
作者
SURYANARAYANA, D [1 ]
HSIAO, R [1 ]
GALL, TP [1 ]
MCCREARY, JM [1 ]
机构
[1] IBM CORP,DIV SYST TECHNOL,TECHNOL LAB,ENDICOTT,NY 13760
来源
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1991年 / 14卷 / 01期
关键词
D O I
10.1109/33.76536
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin having a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of C4 joints in accelerated thermal cycle (ATC) fatigue testing on both low CTE organic and ceramic chip carriers. The C4 joints are encapsulated by dispensing a bead of the resin along an edge of the chip. The encapsulant flows underneath the chip by capillary action and completely fills the gap between the chip and the substrate. Optimization of the filler size distribution and resin rheology to obtain consistent flow under the chip without any bubbles will be discussed. The filler size distribution and flow under the chip are shown in cross sections of several different materials including low alpha emitting encapsulants for memory applications. New encapsulant formulations are tested by videotaping the flow of encapsulant under transparent quartz chips. The formation of bubbles as the encapsulant flows around the C4 joints and irregularities in the surface of the substrate can clearly be seen in the videotape. Proper C4 encapsulation provides virtually complete coverage around all C4 connections. C4 life testing over various temperature ranges shows a 5 to 10 times improvement for both memory and logic footprints when the C4 joints are encapsulated. The vast improvement in C4 joint reliability provided by encapsulation allows the C4 technology to be extended to much larger chips or to higher service temperature ranges without conventional distance from neutral point (DNP) constraints.
引用
收藏
页码:218 / 223
页数:6
相关论文
共 19 条
[1]  
Beckham K. F., 1986, US patent, Patent No. [4,604,644, 4604644]
[2]  
GABRYKEWICZ D, 1986, 1986 P INT S MICR RE, P707
[3]  
GODA M, 1989, Patent No. 4825284
[4]  
GOLDMANN LS, 1969, IBM J RES DEV MAY, P251
[5]  
HATADA K, 1987, INSULATION RESIN BON
[6]  
HORIKOSHI E, 1987, Patent No. 117346
[7]  
HOWARD R, 1981, J ELECTRON MATER, V10, P747
[9]  
Ichikawa K., 1988, Oki Technical Review, V55, P18
[10]  
KOOPMAN NG, 1989, MICROELECTRONICS PAC, P361