A HIGH-PERFORMANCE SI MEMORY CELL

被引:8
|
作者
LEENAERTS, DMW
LEEUWENBURGH, AJ
PERSOON, GG
机构
[1] Department of Electrical Engineering, Technical University of Eindhoven
关键词
D O I
10.1109/4.328642
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to a high accuracy cell with measured errors less than 200 ppm for input currents between 50 and 85 mu A. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies.
引用
收藏
页码:1404 / 1407
页数:4
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