PROOFS - A FAST, MEMORY-EFFICIENT SEQUENTIAL-CIRCUIT FAULT SIMULATOR

被引：73

作者：

NIERMANN, TM ^{[1
]}

CHENG, WT ^{[1
]}

PATEL, JH ^{[1
]}

机构：

[1] UNIV ILLINOIS,CTR RELIABLE & HIGH PERFORMANCE COMP,URBANA,IL 61801

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1992年 / 11卷 / 02期

关键词：

D O I：

10.1109/43.124398

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes PROOFS, a fast fault simulator for synchronous sequential circuits. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. The fault simulator minimizes the memory requirements, reduces the number of gate evaluations, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs six to 67 times faster on the ISCAS-89 sequential benchmark circuits.

引用

页码：198 / 207

页数：10

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