FABRICATION OF NANOMETER-SCALE CONDUCTING SILICON WIRES WITH A SCANNING TUNNELING MICROSCOPE

We report the fabrication of nanometric-scale conducting silicon wires by the STM-induced modification of a passivated silicon (100) surface followed by a selective liquid etch. The modified surface layer is a thin oxide a few monolayers thick which acts as a mask against subsequent liquid etching of the unmodified regions of the silicon surface. Silicon wires as narrow as 30 nm have been fabricated with this technique. More complicated patterns can be written by selectivity pulsing the STM bias to a suitable writing voltage pixel-by-pixel during a low-bias (hence non-exposing) scan. The maximum pattern size is limited by the range of the piezoscanners, which for our system is in excess of 100 mum. Conducting silicon wires between contact pads were fabricated on a silicon layer on top of a buried insulating layer of SiO2 formed by oxygen implantation and subsequent anneal (SIMOX). Backgating of these structures can drive them either into accumulation or inversion, thus allowing independing control of their conductance and carrier type. The techniques described here allow the simple, easy, and reliable fabrication of nanometer-scale devices using relatively inexpensive and widely available equipment.