Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique

Design and analysis of low power, high speed adders is carried out in the present paper. Different full adder circuits are investigated, in terms of power dissipation, propagation delay, power_ delay_ product and power_ delay_ number_ product. Different design styles are compared by circuit simulations. A modified adder design using gate diffusion input technique is proposed, which has less power consumption, higher speed and comparable transistor count as compared to the other adders reported in literature. An eight bit adder is also designed using the proposed 1-bit full adder. The comparative analysis shows that the designed adders have superior performance compared to the reference circuits particularly at the scaled voltages. The results are verified by SPICE simulation for three technology nodes viz. 180 nm, 100 nm and 70 nm.