共 50 条
[31]
Sequential Equivalence Checking of Clock-Gated Circuits
[J].
2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC),
2015,
[32]
Proving Termination via Measure Transfer in Equivalence Checking
[J].
INTEGRATED FORMAL METHODS, IFM 2024,
2025, 15234
:75-84
[34]
On Neural Network Equivalence Checking Using SMT Solvers
[J].
FORMAL MODELING AND ANALYSIS OF TIMED SYSTEMS, FORMATS 2022,
2022, 13465
:237-257
[36]
Fortifying Analog Models with Equivalence Checking and Coverage Analysis
[J].
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE,
2010,
:425-430
[37]
An Equivalence Checking Framework for Array-Intensive Programs
[J].
AUTOMATED TECHNOLOGY FOR VERIFICATION AND ANALYSIS (ATVA 2017),
2017, 10482
:84-90
[38]
Equivalence Checking of Non-Binary Combinational Netlists
[J].
2022 35TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID 2022) HELD CONCURRENTLY WITH 2022 21ST INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (ES 2022),
2022,
:22-27
[39]
Using Logic Synthesis and Circuit Reasoning for Equivalence Checking
[J].
ADVANCED MANUFACTURING SYSTEMS, PTS 1-3,
2011, 201-203
:836-840