HIGH-SPEED 7-BIT A-D CONVERTER

被引:33
作者
VANDEPLASSCHE, RJ
VANDERGRIFT, REJ
机构
[1] Philips Research Laboratories, Eindhoven
关键词
D O I
10.1109/JSSC.1979.1051301
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4 X 2.5 mm. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
引用
收藏
页码:938 / 943
页数:6
相关论文
共 2 条
[1]  
NORDSTROM RA, 1976, ISSCC DIG TECH P FEB, P150
[2]  
PETERSON JG, 1979, ISSCC DIG TECHN FEB, P128