SIMULATION-BASED VERIFICATION FOR HIGH-LEVEL SYNTHESIS

被引：4

作者：

ERNST, R ^{[1
]}

BHASKER, J ^{[1
]}

机构：

[1] AT&T BELL LABS,CAD & TEST LAB,MURRAY HILL,NJ 07974

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1991年 / 8卷 / 01期

关键词：

D O I：

10.1109/54.75659

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The authors describe a way to automatically verify a high-level synthesis system. Their system, called Satya, maps an algorithmic description to a logic circuit description and compares descriptions to detect semantic errors and identify the cause of those errors. The authors have used Satya to verify the Bridge synthesis system, which accepts a subset of C as input, but the simulation-based approach underlying Satya is suitable for verifying synthesis systems that use other high-level languages, such as VHDL.

引用

页码：14 / 20

页数：7