A VLSI-DESIGN FOR FAST VECTOR NORMALIZATION

We describe the design of a high-speed, high-precision single-chip vector normalizer for 3D vectors. It was constructed as a pipelined unit to speed up our graphics system for scientific visualization, but can profitably be employed in any application where a large number of vectors must be processed rapidly. The circuitry accepts 3D vectors with 33 bit two's complement components. The components of the normalized vectors are computed as 16 bit two's complement fixed-point numbers. Due to the overall pipeline architecture, the chip is able to receive one 3D vector and to produce one normalized vector each clock. The architecture was implemented for a clock frequency of 80 MHz using a 0.8 mu m Gate Array technology. The design consumes about 66.500 gates. To normalize a 3D vector, three square operations, two additions, one square root operation and three divisions must be done. Thus, the chip provides a sustained performance of 720 MOPS.