TEST SET COMPACTION FOR COMBINATIONAL-CIRCUITS

被引：56
作者：
CHANG, JS
LIN, CS
机构：
[1] Department of Electrical Engineering, National Taiwan University, Taipei
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1995年 / 14卷 / 11期
关键词：
D O I：
10.1109/43.469663
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set, The special feature is that the given test set will be adaptly renewed to increase the chance of compaction, In the first method,forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage, The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS '85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST.
引用
收藏
页码：1370 / 1378
页数：9
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