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THERMAL-STRESS ANALYSIS WITH ELECTRICAL EQUIVALENTS
被引:0
|
作者
:
RIEMER, DE
论文数:
0
引用数:
0
h-index:
0
机构:
HONEYWELL MSD,EVERETT,WA 98204
HONEYWELL MSD,EVERETT,WA 98204
RIEMER, DE
[
1
]
机构
:
[1]
HONEYWELL MSD,EVERETT,WA 98204
来源
:
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY
|
1990年
/ 13卷
/ 01期
关键词
:
D O I
:
10.1109/33.52870
中图分类号
:
T [工业技术];
学科分类号
:
08 ;
摘要
:
A method is introduced which can help to improve the conceptual understanding of thermal-stress problems, and which is useful for a first-order analysis of thermal stresses in layered structures or laminates. The technique models the thermal expansion and the elasticity of each laminate layer as components in a three-terminal electrical equivalent circuit. A model of the laminate is developed by connecting the electrical equivalent circuits of the layers in a network. Currents and voltages are obtained by a network analysis. The thermal stresses in the laminate are derived from the branch currents, the local thermal expansion coefficients for the surfaces or for internally bonded interfaces are given by the node voltages. © 1990 IEEE.
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页码:194 / 199
页数:6
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