A CMOS RISC CPU DESIGNED FOR SUSTAINED HIGH-PERFORMANCE ON LARGE APPLICATIONS

被引:1
|
作者
LOTZ, J
MILLER, B
DELANO, E
LAMB, J
FORSYTH, M
HOTCHKISS, T
机构
[1] Hewlett-Packard Company, Fort Collins, CO
关键词
D O I
10.1109/4.62141
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAM’s. Key performance features include a 3.5-ns 32-b adder, low skew on chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0- μm CMOS process that utilizes three-level metal and 480 000 transistors on a 14 ×14-mm die. © 1990 IEEE
引用
收藏
页码:1190 / 1198
页数:9
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