SINGLE EVENT UPSET TEST STRUCTURES FOR DIGITAL CMOS APPLICATION-SPECIFIC INTEGRATED-CIRCUITS

被引：2
作者：
BAZE, MP
BARTHOLET, WG
BRAATZ, JC
DAO, TA
机构：
[1] Boeing Defense and Space Group, Seattle, Wa., 98124
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1993年 / 40卷 / 06期
关键词：
D O I：
10.1109/23.273490
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An approach has been developed for the design and utilization of SEU test Structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips
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页码：1703 / 1708
页数：6
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