IMPROVING MULTIPLIER DESIGN BY USING IMPROVED COLUMN COMPRESSION TREE AND OPTIMIZED FINAL ADDER IN CMOS TECHNOLOGY

被引：60

作者：

OKLOBDZIJA, VG ^{[1
]}

VILLEGER, D ^{[1
]}

机构：

[1] ECOLE SUPER INGN ELECTROTECH & ELECTR,F-93162 NOISY LE GRAND,FRANCE

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 1995年 / 3卷 / 02期

关键词：

D O I：

10.1109/92.386228

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier.

引用

页码：292 / 301

页数：10