DESIGN OF A NOVEL ARRAY MULTIPLIER USING ADIABATIC LOGIC IN 32NM CMOS TECHNOLOGY

Aim: The paper presents a new adiabatic multiplier circuit based on Complementary Energy Path Adiabatic Logic(CEPAL). The proposed multiplier consumes lesser power when compared to the conventional CMOS multiplier. The proposed adiabatic array multiplier performs 8 bit multiplication. The proposed adiabatic multiplier is also designed with leakage reduction technique the performnance of which is better when compared to the CMOS multiplier. The operating speed of the complementary metal oxide semidonductor is increased. This paper presents the implementation of adiabatic CEPAL multiplier using CMOS. The measurement results of the adiabatic CMOS Multiplier demonstrates a reduction in power and reduction in energy. The operating frequency is in GHz range. These results shows that the propoed circuit can be used in high speed application. The proposed adiabatic circuits are designed in HSPICE using predictive technology models (PTM) in 32nm CMOS Technology. The experimental results for the proposed adiabatic designs demonstrate their effectiveness with energy consumption and with power optimization.