LATENT INTERFACE-TRAP BUILDUP AND ITS IMPLICATIONS FOR HARDNESS ASSURANCE

Long term anneals at temperatures from 25-degrees-C to 135-degrees-C have been performed on irradiated MOS transistors. Following the ''normal'' saturation of interface-trap density (within 10(2) to 10(5) s after irradiation), large increases in the number of interface traps have been observed for both commercial and radiation-hardened transistors at very long times after irradiation (>10(6) s at 25-degrees-C). This ''latent'' buildup of interface traps can be significant, up to a factor of four times larger than the normal saturation value. The latent buildup is thermally activated with an activation energy of 0.47 +/- 0.08 eV. As a natural consequence of the delay between the normal and the latent buildup, there is a ''window'' in time in which little or no interface-trap buildup occurs. Two possible mechanisms for the latent buildup are explored: 1) the direct conversion of oxide traps into interface traps or ''border traps'' and 2) the diffusion of molecular hydrogen into the gate oxide from adjacent structures. The latent buildup of interface traps can degrade the performance of ICs in space systems and may cause IC failure at long times. Interface-trap windows can present problems in measuring and predicting the number of interface traps at very late times using a typical rebound test, e.g., that of MIL-STD-883D, Test Method 1019.4. Recommendations are provided for characterizing latent interface-trap buildup.