A HIGH-PERFORMANCE BICMOS TECHNOLOGY WITH DOUBLE-POLYSILICON SELF-ALIGNED BIPOLAR-DEVICES

被引：5
|
作者：
RAJKANAN, K
GHEEWALA, TR
DIEDRICK, J
机构：
来源：
IEEE ELECTRON DEVICE LETTERS | 1987年 / 8卷 / 11期
关键词：
D O I：
10.1109/EDL.1987.26711
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：509 / 511
页数：3
相关论文
共 50 条
  • [41] A V-GROOVE EMITTER SELF-ALIGNED BIPOLAR TECHNOLOGY
    HEBERT, F
    SOLHEIM, AG
    ROULSTON, DJ
    SOLID-STATE ELECTRONICS, 1988, 31 (10) : 1558 - 1560
  • [42] The design and fabrication of 0.35 μm single-polysilicon self-aligned bipolar transistors
    Chantre, A
    Gravier, T
    Niel, S
    Kirtsch, J
    Granier, A
    Grouillet, A
    Guillermet, A
    Maury, D
    Pantel, R
    Regolini, JL
    Vincent, G
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (4A): : 1781 - 1786
  • [43] A NONRECESSED-BASE, SELF-ALIGNED BIPOLAR STRUCTURE WITH SELECTIVELY DEPOSITED POLYSILICON EMITTER
    SUN, SW
    DENNING, D
    HAYDEN, JD
    WOO, M
    FITCH, JT
    KAUSHIK, V
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (07) : 1711 - 1716
  • [44] Design and fabrication of 0.35 μm single-polysilicon self-aligned bipolar transistors
    Chantre, Alain
    Gravier, Thierry
    Niel, Stephan
    Kirtsch, Jean
    Granier, Andre
    Grouillet, Andre
    Guillermet, Marc
    Maury, Delphine
    Pantel, Roland
    Regolini, Jorge Luis
    Vincent, Gilbert
    1781, JJAP, Tokyo, Japan (37):
  • [45] A HIGH-PERFORMANCE SELF-ALIGNED UMOSFET WITH A VERTICAL TRENCH CONTACT STRUCTURE
    MATSUMOTO, S
    OHNO, T
    ISHII, H
    YOSHINO, H
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (05) : 814 - 818
  • [46] NONOVERLAPPING SUPER SELF-ALIGNED DEVICE STRUCTURE FOR HIGH-PERFORMANCE VLSI
    CHIU, TY
    CHIN, GM
    LAU, MY
    HANSON, RC
    MORRIS, MD
    LEE, KF
    VOSHCHENKOV, AM
    SWARTZ, RG
    ARCHER, VD
    LIU, MTY
    FINEGAN, SN
    FEUER, MD
    IEEE ELECTRON DEVICE LETTERS, 1990, 11 (02) : 85 - 87
  • [47] Very high speed bipolar integrated circuit process using self-aligned technology
    Sawada, Shigeki
    Nishiura, Shinji
    Manabe, Kenji
    National technical report, 1990, 36 (04): : 90 - 96
  • [48] HIGH-PERFORMANCE SELF-ALIGNED (AL,GA)AS/(IN,GA)AS PSEUDOMORPHIC HIGFETS
    ABROKWAH, JK
    STEPHENS, JM
    IEEE ELECTRON DEVICE LETTERS, 1989, 10 (05) : 225 - 226
  • [49] AN ULTRA-HIGH-SPEED ECL-BICMOS TECHNOLOGY WITH SILICON FILLET SELF-ALIGNED CONTACTS
    LIU, TYM
    CHIN, GM
    JEON, DY
    MORRIS, MD
    ARCHER, VD
    JOHNSON, RW
    TARSIA, M
    KIM, HH
    CERULLO, M
    LEE, KF
    SUNG, JMJ
    LAU, KS
    CHIU, TY
    VOSHCHENKOV, AM
    SWARTZ, RG
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (09) : 1546 - 1555
  • [50] HIGH-SPEED BIPOLAR ICS USING SUPER SELF-ALIGNED PROCESS TECHNOLOGY
    SAKAI, T
    KOBAYASHI, Y
    YAMAUCHI, H
    SATO, M
    MAKINO, T
    JAPANESE JOURNAL OF APPLIED PHYSICS, 1981, 20 (01) : 155 - 159
12345