LOW-POWER BUILDING-BLOCK FOR ARTIFICIAL NEURAL NETWORKS

被引：9

作者：

LEE, ST

LAU, KT

机构：

[1] Microelectronics Centre, School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 19期

关键词：

NEURAL NETWORKS; INTEGRATED CIRCUITS;

D O I：

10.1049/el:19951138

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The authors propose and analyse a low-power CMOS building block for artificial neural networks (ANNs) that can function either as a synapse or a neuron. The design is based on the current-mode approach and uses the square-law characteristics of a MOS transistor working in saturation. The new building block uses I-V converters, a current-mirror and a +/- 1 V power supply to achieve superior performance, Modularity, ease of interconnectivity, expandability and reconfigurability are the advantages of this building block.

引用

页码：1618 / 1619

页数：2