SCHEDULING FOR PERIODIC CONCURRENT ERROR-DETECTION IN PROCESSOR ARRAYS

Periodic application of time-redundant error checking to processor arrays provides a trade-off between error detection latency and performance degradation. The goal is to achieve high error coverage while satisfying performance requirements. In this paper, we derive the optimal scheduling of checking patterns for linear processor arrays in order to minimize the error detection latency and maximize the error coverage. (C) 1994 Academic Press, Inc.