SCHEDULING FOR PERIODIC CONCURRENT ERROR-DETECTION IN PROCESSOR ARRAYS

被引：3

作者：

WANG, YM ^{[1
]}

CHUNG, PY ^{[1
]}

FUCHS, WK ^{[1
]}

机构：

[1] UNIV ILLINOIS,COORDINATED SCI LAB,URBANA,IL 61801

来源：

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING | 1994年 / 23卷 / 03期

关键词：

D O I：

10.1006/jpdc.1994.1142

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Periodic application of time-redundant error checking to processor arrays provides a trade-off between error detection latency and performance degradation. The goal is to achieve high error coverage while satisfying performance requirements. In this paper, we derive the optimal scheduling of checking patterns for linear processor arrays in order to minimize the error detection latency and maximize the error coverage. (C) 1994 Academic Press, Inc.

引用

页码：306 / 313

页数：8

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