FULL CMOS VIDEO LINE-LOCKED PHASE-LOCKED LOOP SYSTEM

被引：3

作者：

RODDA, WE ^{[1
]}

CAMPBELL, ER ^{[1
]}

SAUER, DJ ^{[1
]}

MAYWEATHER, WT ^{[1
]}

DELLOVA, F ^{[1
]}

机构：

[1] THOMSON CONSUMER ELECT COMPONENTS,MEYLAN,FRANCE

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1993年 / 39卷 / 03期

关键词：

D O I：

10.1109/30.234626

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS PLL system for generation of a television line-locked clock in the frequency range 25 MHz to 40 MHz is described. The PLL system is designed for use as a generic building block with large scale CMOS video signal processing integrated circuits. The development of a custom test chip version of the PLL system is reported.

引用

页码：496 / 503

页数：8

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