AN ADAPTIVE TIMING-DRIVEN PLACEMENT FOR HIGH-PERFORMANCE VLSIS

被引：2
作者：
SUTANTHAVIBUL, S
SHRAGOWITZ, E
LIN, RB
机构：
[1] IBM CORP, DIV ENTERPRISE SYST, KINGSTON, NY 12401 USA
[2] UNIV MINNESOTA, DEPT COMP SCI, MINNEAPOLIS, MN 55455 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1993年 / 12卷 / 10期
关键词：
D O I：
10.1109/43.256922
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes an application of constructive successive augmentation methodology to VLSI placement under constraints on routability, area and timing. To improve effectiveness of decision making, the placement algorithm uses adaptive and look-ahead procedures. This methodology was implemented in the placer-router JUNE for macrocell-library-based sea-of-gates design style with over-the-cell routing. JUNE achieves high utilization of area and timing requirements for real-life designs.
引用
收藏
页码：1488 / 1498
页数：11
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