HARDWARE APPROACHES TO CACHE COHERENCE IN SHARED-MEMORY MULTIPROCESSORS, .1.

被引：18
|
作者：
TOMASEVIC, M
MILUTINOVIC, V
机构：
[1] UNIV BELGRADE,SCH ELECT ENGN,YU-11000 BELGRADE,YUGOSLAVIA
[2] MIHAILO PUPIN INST,BELGRADE,YUGOSLAVIA
来源：
IEEE MICRO | 1994年 / 14卷 / 05期
关键词：
D O I：
10.1109/MM.1994.363067
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions with an ability to achieve high performance. We discuss the principles of the two major groups of hardware protocols and summarize relevant representatives. In Part 2 of this two-part series, we also consider the coherence problem in multilevel caches and cache coherence maintenance in large-scale shared-memory multiprocessors.
引用
收藏
页码：52 / 59
页数：8
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