HARDWARE APPROACHES TO CACHE COHERENCE IN SHARED-MEMORY MULTIPROCESSORS, .1.

Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions with an ability to achieve high performance. We discuss the principles of the two major groups of hardware protocols and summarize relevant representatives. In Part 2 of this two-part series, we also consider the coherence problem in multilevel caches and cache coherence maintenance in large-scale shared-memory multiprocessors.