MULTICARRIER DEMODULATOR ARCHITECTURE FOR ONBOARD PROCESSING SATELLITES

A parallel pipelined architecture is presented for demultiplexing and demodulating single channel per carrier/frequency division multiple access (SCPC/FDMA) channels in real time. Specific algorithms are selected for each of the operations necessary for multicarrier demodulation. The selection is made based on their suitability for implementation into parallel-pipelined and sharing schemes. The algorithms are analyzed for data dependencies and divided into data dependent and independent sections. The segregated sections are mapped by implementing the independent sections in a parallel scheme and the dependent sections in a pipelined scheme. The demultiplexing is performed by the polyphase fast Fourier transform (FFT) method, which requires a bank of filters followed by an FFT operation. A shared filter bank module and a pipelined FFT module are designed to implement the bank of filters and the FFT operation, respectively. The demodulator uses a single hardware module that is shared amongst all of the channels for the recovery of timing, carrier, and data. This sharing of hardware to perform the demultiplexing and demodulating of all of the channels results in savings of power and hardware. The system is suitable for onboard processing of signals in satellites where power and ares requirements are critical. The architecture is also highly modular and therefore lends itself well to very large scale integration (VLSI) implementation. This design is illustrated for the specific case of processing 800 FDMA channels at 64 kbps each.