AN ANALYTIC IV MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES

[1] ELECTRON-MOBILITY EMPIRICALLY RELATED TO PHOSPHORUS CONCENTRATION IN SILICON [J]. SOLID-STATE ELECTRONICS, 1975, 18 (06) : 579 - 580

[2] LIGHTLY DOPED DRAIN TRANSISTORS FOR ADVANCED VLSI CIRCUITS [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (05) : 896 - 902

[3] AN ANALYTICAL METHOD FOR DETERMINING INTRINSIC DRAIN SOURCE RESISTANCE OF LIGHTLY DOPED DRAIN (LDD) DEVICES [J]. SOLID-STATE ELECTRONICS, 1984, 27 (01) : 89 - 96

[4] AN ANALYTICAL ONE-DIMENSIONAL MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (12) : 2803 - 2811

[5] ACCURATE LARGE-SIGNAL MOS TRANSISTOR MODEL FOR USE IN COMPUTER-AIDED DESIGN [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1972, ED19 (05) : 681 - +

[6] DESIGN AND CHARACTERISTICS OF THE LIGHTLY DOPED DRAIN-SOURCE (LDD) INSULATED GATE FIELD-EFFECT TRANSISTOR [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) : 1359 - 1367

[7] Schutz A., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P766

[8] A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS [J]. SOLID-STATE ELECTRONICS, 1985, 28 (12) : 1283 - 1289

[9] AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION [J]. SOLID-STATE ELECTRONICS, 1985, 28 (12) : 1271 - 1278

[10] AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION [J]. SOLID-STATE ELECTRONICS, 1986, 29 (04) : 387 - 394

[1] ELECTRON-MOBILITY EMPIRICALLY RELATED TO PHOSPHORUS CONCENTRATION IN SILICON [J]. SOLID-STATE ELECTRONICS, 1975, 18 (06) : 579 - 580

[2] LIGHTLY DOPED DRAIN TRANSISTORS FOR ADVANCED VLSI CIRCUITS [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (05) : 896 - 902

[3] AN ANALYTICAL METHOD FOR DETERMINING INTRINSIC DRAIN SOURCE RESISTANCE OF LIGHTLY DOPED DRAIN (LDD) DEVICES [J]. SOLID-STATE ELECTRONICS, 1984, 27 (01) : 89 - 96

[4] AN ANALYTICAL ONE-DIMENSIONAL MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (12) : 2803 - 2811

[5] ACCURATE LARGE-SIGNAL MOS TRANSISTOR MODEL FOR USE IN COMPUTER-AIDED DESIGN [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1972, ED19 (05) : 681 - +

[6] DESIGN AND CHARACTERISTICS OF THE LIGHTLY DOPED DRAIN-SOURCE (LDD) INSULATED GATE FIELD-EFFECT TRANSISTOR [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) : 1359 - 1367

[7] Schutz A., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P766

[8] A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS [J]. SOLID-STATE ELECTRONICS, 1985, 28 (12) : 1283 - 1289

[9] AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION [J]. SOLID-STATE ELECTRONICS, 1985, 28 (12) : 1271 - 1278

[10] AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION [J]. SOLID-STATE ELECTRONICS, 1986, 29 (04) : 387 - 394