DESIGN OF SUB SAMPLING FILTER ARCHITECTURE FOR DISCRETE WAVELET TRANSFORM

Power dissipation and area reduction is the main constraint in the present scenario of VLSI circuits. The power dissipation of the circuit is mainly due to static or leakage power. The leakage power contributes to about 50% of the power dissipation in all the devices that are used in our day to day life. Discrete Wavelet Transform (DWT) has more advantages compared with FFT and DCT and it has many applications. Design of VLSI architecture of DWT is very important in the present scenario. To get better efficiency and throughput, DWT architecture is proposed with sub sampling filter with array multiplier and ripple carry adder. In the existing system, Carry save adder and Bough Wooley multiplier were used to design a subsampling filters, resulting that the power dissipation and number of transistors required are more which leads to complexity. In the proposed method the number of transistors required to design the sub sampling filter and power dissipation are measured using LTSpice IV tool which is less compared with existing filter.