Design and implementation of the JPEG algorithm in integrated circuit

The JPEG compression algorithm is widely used in applications demanding transfer or storage of digital images and also in cameras of mobile phones. There are rigorous constraints imposed on integrated circuits of mobile phones in terms of their price and power consumption. Software implementations of the JPEG algorithm normally require storing the image in an uncompressed form before processing. In case of a 3-Mpixel image size, this requires a memory capacity of 6 MB. The hardware implementation of the JPEG algorithm described in this paper performs the compression simultaneously with the image captured from the image sensor. As this eliminates the need of the memory, and consequently reduces the chip area, the cost and power consumption of the integrated circuit, the proposed hardware implementation proves to be an optimal solution for the use in mobile phones. The designed JPEG integrated circuit, realized in the 90 nm technology with ISP (Image Signal Processing) and JPEG functionality, performs the complete image processing and sensor control as well as image compression inside the JPEG module.