EFFICIENT TESTS FOR CMOS VLSI CIRCUITS

A new concept, the path testing approach, is introduced in this paper. This approach leads to the simultaneous testing of a set of MOS transistors in a particular path in a CMOS circuit instead of individual ones. Using this concept, we generate two procedures, one based on the Karnaugh map and the other based on a modified Quine-McCluskey tabular approach, to identify a minimal robust test set for a direct CMOS complementary gate. The test set derived from these procedures is implementation independent, and it can be used for detecting both single and multiple faults.