EFFICIENT TESTS FOR CMOS VLSI CIRCUITS

被引：0

作者：

RADHAKRISHNAN, D ^{[1
]}

LAI, CM ^{[1
]}

机构：

[1] NATL SEMICOND CORP,SANTA CLARA,CA 95052

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 1991年 / 71卷 / 01期

基金：

美国国家航空航天局;

关键词：

D O I：

10.1080/00207219108925456

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new concept, the path testing approach, is introduced in this paper. This approach leads to the simultaneous testing of a set of MOS transistors in a particular path in a CMOS circuit instead of individual ones. Using this concept, we generate two procedures, one based on the Karnaugh map and the other based on a modified Quine-McCluskey tabular approach, to identify a minimal robust test set for a direct CMOS complementary gate. The test set derived from these procedures is implementation independent, and it can be used for detecting both single and multiple faults.

引用

页码：29 / 43

页数：15

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