A FLEXIBLE MULTIPORT RAM COMPILER FOR DATA PATH

被引:10
作者
SHINOHARA, H
MATSUMOTO, N
FUJIMORI, K
TSUJIHASHI, Y
NAKAO, H
KATO, S
HORIBA, Y
TADA, A
机构
[1] MITSUBISHI ELECTR CO,CTR ASIC DESIGN ENGN,ITAMI,HYOGO 664,JAPAN
[2] OKAYAMA UNIV SCI,DEPT ELECTR,OKAYAMA 770,JAPAN
[3] MITSUBISHI ELECTR CO,KITAITAMI WORKS,ITAMI,HYOGO 664,JAPAN
[4] MITSUBISHI ELECTR CO,LSI RES & DEV LAB,DEPT VLSI DEVICE DEV 2,ITAMI,HYOGO 664,JAPAN
关键词
13;
D O I
10.1109/4.75013
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-mu-m CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words x 16 b and 512 words x 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.
引用
收藏
页码:343 / 349
页数:7
相关论文
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