LOGIC CIRCUIT PACKAGE DESIGN

[1] KAWAMATA A, 1969, REV ELEC COMMUN LAB, V17, P1317

[2] KUSUNOKI K, 1969, REV ELEC COMMUN LAB, V17, P1281

[3] Lee CY, 1961, IRE T ELECTRON COMPU, VEC-10, P346, DOI DOI 10.1109/TEC.1961.5219222

[4] MOOR E, 1959, ANNALS COMPUTATION L, P282

[5] PROGRAMMED ALGORITHMS TO COMPUTE TESTS TO DETECT AND DISTINGUISH BETWEEN FAILURES IN LOGIC CIRCUITS [J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (05): : 567 - +

[6] Seshu S., 1962, IRE T ELECTRON COMPU, VEC-11, P459

[1] KAWAMATA A, 1969, REV ELEC COMMUN LAB, V17, P1317

[2] KUSUNOKI K, 1969, REV ELEC COMMUN LAB, V17, P1281

[3] Lee CY, 1961, IRE T ELECTRON COMPU, VEC-10, P346, DOI DOI 10.1109/TEC.1961.5219222

[4] MOOR E, 1959, ANNALS COMPUTATION L, P282

[5] PROGRAMMED ALGORITHMS TO COMPUTE TESTS TO DETECT AND DISTINGUISH BETWEEN FAILURES IN LOGIC CIRCUITS [J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (05): : 567 - +

[6] Seshu S., 1962, IRE T ELECTRON COMPU, VEC-11, P459