Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon

Increased static and dynamic power dissipation in the integrated circuits (ICs) are the main obstacle for growing demands of smart phones and laptops, which require semiconductor devices having low power operation. As the conventional MOSFET has a thermodynamic limit of 60 mV/decade at 300 K on subthreshold slope (SS), so the device based on the mechanism other than diffusion over a thermal barrier came into existence. In this regard, Tunnel-FET (TFET) has emerged as a promising replacement. Due to its lower subthreshold slope (<60 mV/decade at 300 K), reduced OFF-current (I-OFF), reduced power consumption, and negligible short channel effects, TFETs have achieved a lot of attention in the recent years. In the present research work, double-gate TFET (DG-TFET) device has been investigated. The simulation result shows a very good I-ON/I-OFF ratio (10(12)) and low SS (similar to 41.54 mV/dec). The DG-TFET has very low off current, I-OFF (similar to 10(-17) A/mu m) and ON-current of (I-ON) similar to 10(-5) (A/mu m) using gate bias in the vicinity of 0.5 V. In addition, we have optimized the device parameters, thus improving the I-ON current and the I-ON/I-OFF ratio yield for two kinds of technologies (using HfO2 or SiO2 as gate dielectric). A comparison between the two technologies was made. Gate to drain (C-gd) capacitance as function of gate to source voltage V-GS as well as drain to source voltage V-DS at frequency f = 1 MHz, C-gd is weaker using SiO2 as gate dielectric compared to HfO2.