Simulation of Wafer-Scale GTO Thyristors in Circuits

被引：7

作者：

Johnson, C. Mark ^{[1
]}

Palmer, Patrick R. ^{[1
]}

机构：

[1] Univ Cambridge, Dept Engn, Trumpington St, Cambridge CB2 1PZ, England

来源：

IEEE TRANSACTIONS ON POWER ELECTRONICS | 1991年 / 6卷 / 02期

关键词：

D O I：

10.1109/63.76818

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simulation technique has been developed that allows the study of large area power devices composed of many, outwardly identical elements operating in a realistic power circuit. Results are presented showing the transient redistribution of current between a pair of GTO thyristor elements during turn-off under the influence of the power circuit. The method is validated by comparing simulated results with experimental measurements. Variations in carrier lifetime, diffusion uniformity and gate contact position are studied and they are shown to significantly alter the turn-off performance. Conclusions are then drawn concerning the reliability of large area latching power devices with process inhomogeneity.

引用

页码：308 / 313

页数：6

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