SIMPLE NOISE MODEL AND LOW-NOISE DATA-OUTPUT BUFFER FOR ULTRAHIGH-SPEED MEMORIES

被引：4

作者：

WADA, T ^{[1
]}

EINO, M ^{[1
]}

ANAMI, K ^{[1
]}

机构：

[1] MITSUBISHI ELECTR CO,KITA ITAMI WORKS,ITAMI,HYOGO 664,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 06期

关键词：

D O I：

10.1109/4.62195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analytic noise (voltage bounce on chip-internal Vec/GND lines) model for data-output buffers is described. The model indicates that tr (switching time of output transistor) greater than L X G0 (product between the parasitic inductance on Vec/GND lines and the conductance of the output transistor) and small output voltage amplitude are required in order to reduce the noise voltage. The model gives VLSI circuit designers a rough estimation of the Vec/GND line noise. A low-noise data-output buffer combined with a voltage down converter (VDC) is newly proposed. It decreases the peak noise voltage by one-half without degrading the access time. © 1990 IEEE

引用

页码：1586 / 1588

页数：3