A CURRENT-CONTROLLED LATCH SENSE AMPLIFIER AND A STATIC POWER-SAVING INPUT BUFFER FOR LOW-POWER ARCHITECTURE

被引：182

作者：

KOBAYASHI, T ^{[1
]}

NOGAMI, K ^{[1
]}

SHIROTORI, T ^{[1
]}

FUJIMOTO, Y ^{[1
]}

机构：

[1] TOSHIBA MICROELECTR CORP,SAIWAI KU,KAWASAKI 210,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1993年 / 28卷 / 04期

关键词：

D O I：

10.1109/4.210039

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes two new power-saving schemes for high-performance VLSI's with a large-scale memory and many interface signals. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces dc current in interface circuits receiving TTL-high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM.

引用

页码：523 / 527

页数：5

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NOGAMI, K ;

SHIROTORI, T ;

FUJIMOTO, Y ;

BIWAKI, Y ;

NOHARA, H ;

KOBAYASHI, M ;

KOBAYASHI, K ;

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