The Hardware Design for a Genetic Algorithm Accelerator for Packet Scheduling Problems

被引:0
|
作者
Lee, Yang-Han [1 ]
Jan, Yih-Guang [1 ]
Chou, Yun-Hsih [2 ]
Tseng, Hsien-Wei [1 ]
Chuang, Ming-Hsueh [1 ]
Sheu, Shiann-Tsong [3 ]
Chuang, Yue-Ru [1 ]
Shen, Jei-Jung [1 ]
Fan, Chun-Chieh [4 ]
机构
[1] Tamkang Univ, Dept Elect Engn, Tamsui 251, Taiwan
[2] St Johns Univ, Dept Elect Engn, Tamsui 251, Taiwan
[3] Natl Cent Univ, Dept Commun Engn, Taoyuan 320, Taiwan
[4] St Johns Univ, Dept Comp & Commun Engn, Tamsui 251, Taiwan
来源
JOURNAL OF APPLIED SCIENCE AND ENGINEERING | 2008年 / 11卷 / 02期
关键词
Genetic Algorithm; Packet Scheduling; Base Generator; Operation Selector; Delta Calculator; Duplicate Priority Encoder; Abort Priority Encoder; Next Generator;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In the basic genetic algorithm and its variations, they usually process the calculations in a sequential way so that the waiting time for every generation member awaited to be processed increases dramatically when the generation evolution continues. Consequently the algorithm converging rate becomes a serious problem when we try to apply the genetic algorithm in real time system operations such as in the packet scheduling and channels assignment in the fiber optic networks. We first propose in this paper a genetic algorithm accelerator which has the capability not only to accelerate the algorithm convergent rate but also to have its solution to reach the problem's optimum solution. Then we develop hardware blocks such as the blocks of Base Generator, Operation Selector, Delta Calculator, Duplicate Priority Encoder, Abort Priority Encoder and Next Generator, etc. to realize this proposed generic algorithm accelerator. Due to these hardware blocks realizations it will enhance the speed of the algorithm converging rate and make certain its convergent solution reaches the problem's optimum solution.
引用
收藏
页码:165 / 174
页数:10
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