A High Linearity ADC with a ramp kickback noise compensation technique integrated in CIS

According to the CMOS image sensor ( CIS) high linearity, low power consumption, and consistent loading requirement, this paper proposed an analog-to-digital-converter ( ADC) implement circuit that integrated in CIS. The proposed ADC aims to achieve high linearity as well as low power consumption or consistent power source loading. In the readout chain, every column has an independent programmable-gain-amplifier (PGA), an ADC comparator, and an ADC counter. However, all the columns share a ramp generator to provide a ramp reference to the ADC comparator. The proposed high linearity ADC is optimized through a ramp kickback noise compensation technique, a load balance technique. In addition, low power consumption mode is an optional for circumstance requires low power consumption.