WAFER BONDING TECHNOLOGY FOR SILICON-ON-INSULATOR APPLICATIONS - A REVIEW

被引：33

作者：

MITANI, K ^{[1
]}

GOSELE, UM ^{[1
]}

机构：

[1] SHIN ETSU HANDOTAI RES & DEV,ANNAKA,GUNMA 37901,JAPAN

来源：

JOURNAL OF ELECTRONIC MATERIALS | 1992年 / 21卷 / 07期

关键词：

WAFER BONDING; BONDING INTERFACE; BONDING STRENGTH; BUBBLES; SILICON-ON-INSULATOR (SOI); POLISH-STOP; ETCH-STOP; MICRO-CLEANROOM SET-UP; CRACK-OPENING METHOD;

D O I：

10.1007/BF02655594

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The status of wafer bonding technology especially for silicon-on-insulator (SOI) materials is reviewed. General advantages of wafer bonding as well as specific problems of wafer bonding, such as interface bubble formation, and solutions for these problems are discussed. The specific requirements for SOI materials in terms of SOI layer thickness and the appropriate thinning procedures are dealt with. Interface properties such as bonding strength and electrical properties are also reviewed. Various device results are mentioned.

引用

页码：669 / 676

页数：8

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