REDUNDANCY IN LSI MEMORY ARRAY

被引：12

作者：

CHEN, A

机构：

[1] Information Sciences Laboratory, General Electric Company, Schenectady

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1969年 / SC 4卷 / 05期

关键词：

D O I：

10.1109/JSSC.1969.1050019

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The probability of array yield for a large-scale integrated (LSI) memory array is considered. The calculation assumes the random distribution of defective cells and the discretionary wiring of good rows and columns. Under the above conditions, the calculation shows that the most efficient use of redundancy is to have more row or column redundancy along the longer dimension of the array. Copyright © 1969 by The Instrtute of Electrical and Electronics Engineers, Inc.

引用

页码：291 / &