A ONE-CHIP SCALABLE 8-STAR-8 ATM SWITCH LSI EMPLOYING SHARED BUFFER ARCHITECTURE

This paper presents a one-chip scalable 8 * 8 shared buffer switch LSI, which includes a 256 cell buffer. Speeding-up, flow control, and input slot rotation functions are provided in order to interconnect LSI's for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result. These functions can make the cell loss rate for a Clos 3-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8-mu BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated.