MINIMIZING PRODUCTION TEST TIME TO DETECT FAULTS IN ANALOG CIRCUITS

被引:96
作者
MILOR, L
SANGIOVANNIVINCENTELLI, AL
机构
[1] UNIV MARYLAND,INST SYST RES,COLLEGE PK,MD 20742
[2] UNIV CALIF BERKELEY,DEPT ELECT ENGN & COMP SCI,BERKELEY,CA 94720
关键词
D O I
10.1109/43.285252
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Analog testing is a difficult task without a clear-cut methodology. Analog circuits are tested for satisfying their specifications, not for faults, Given the high cost of testing analog specifications, it is proposed that tests for analog circuits should be designed to detect faults. Therefore analog fault modeling is discussed. Based on an analysis of the types of tests needed for different types of faults, algorithms for fault-driven test set selection are presented. A major reduction in testing time should come from reducing the number of specification tests that need to be performed. Hence algorithms are presented for minimizing specification testing time. After specification testing time is minimized, the resulting test sets are supplemented with some simple, possibly non-specification, tests to achieve 100% fault coverage. Examples indicate that fault-driven test set development can lead to drastic reductions in production testing time.
引用
收藏
页码:796 / 813
页数:18
相关论文
共 26 条
[1]  
ANTONIADIS DA, 1978, 50192 STANF EL LAB T
[2]  
BANERJEE P, 1982, SEP P IEEE INT C CIR, P564
[3]  
BOX GEP, 1978, STATISTICS EXPT
[4]   PREDICTIVE SUBSET TESTING - OPTIMIZING IC PARAMETRIC PERFORMANCE TESTING FOR QUALITY, COST, AND YIELD [J].
BROCKMAN, JB ;
DIRECTOR, SW .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1989, 2 (03) :104-113
[5]   A MACROMODELING ALGORITHM FOR ANALOG CIRCUITS [J].
CASINOVI, G ;
SANGIOVANNIVINCENTELLI, A .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (02) :150-160
[6]  
CHAO CY, 1992, PROCEEDINGS OF THE 35TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, P927, DOI 10.1109/MWSCAS.1992.271146
[7]  
HUSS SD, UNPUB OPTIMAL SELECT
[8]  
HUSS SD, 1991, P DES AUT C, P494
[9]   CONSISTENCY CHECKING AND OPTIMIZATION OF MACROMODELS [J].
JU, YC ;
RAO, VB ;
SALEH, RA .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (08) :957-967
[10]   HIERARCHICAL YIELD ESTIMATION OF LARGE ANALOG INTEGRATED-CIRCUITS [J].
KURKER, CM ;
PAULOS, JJ ;
GYURCSIK, RS ;
LU, JC .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (03) :203-209