A SILICON VERTICAL JFET COMPATIBLE WITH STANDARD 0.7-MU-M CMOS TECHNOLOGY

被引：3

作者：

GRANIER, A

MOUIS, M

DEGORS, N

KIRTSCH, J

CHANTRE, A

机构：

[1] France Telecom, CNET, CNS, F-38243 Meylan Cedex

[2] affiliated to the Institut d'Electronique Fondamentale, CNRS URA 22

来源：

MICROELECTRONIC ENGINEERING | 1992年 / 19卷 / 1-4期

关键词：

Interdigited masks - Parasitic capacitances - Vertical JFET;

D O I：

10.1016/0167-9317(92)90398-B

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports the fabrication of vertical junction field-effect transistors (v-JFETs) with standard 0.7 mum CMOS technology. The process flow is described and the device feasibility is demonstrated. The measured electrical and frequency performances are in good agreement with the simulation results when parasitic capacitances, inherent to the non-optimised layout presently used, are taken into account. It is shown that, with a specific interdigited mask design, a transit frequency higher than 10 GHz could be achieved with a 1.6 mum periodicity.

引用

页码：83 / 88

页数：6