ANALYSIS AND MODELING OF PARASITIC SUBSTRATE COUPLING IN CMOS CIRCUITS

被引：18

作者：

ARAGONES, X ^{[1
]}

MOLL, F ^{[1
]}

ROCA, M ^{[1
]}

RUBIO, A ^{[1
]}

机构：

[1] UNIV ILLES BALEARS,FAC SCI,DEPT PHYS,E-07071 PALMA DE MALLORCA,SPAIN

来源：

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 1995年 / 142卷 / 05期

关键词：

CMOS TECHNOLOGY; PARASITIC CAPACITANCES; SUBSTRATE NOISE ANALYSIS; MIXED-SIGNAL CIRCUITS; RAM ERRORS; VLSI;

D O I：

10.1049/ip-cds:19952164

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed.

引用

页码：307 / 312

页数：6

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