This letter proposes a new level-shifting structure that can convert extremely low levels of input voltages to high output voltages while maintaining excellent delay and power dissipation. In order to reduce contention and voltage swing in the internal nodes, the proposed circuit uses a diode-connected level shifter between gate terminals of the output inverter. Using a control circuit, only during the high-to-low transitions of the output, a current is forced into the diode-connected device. Measurement results demonstrate that the proposed circuit can consume as small energy as 4.2 fJ/transition with V-DDL and V-DDH of 0.35 V and 1.1 V, respectively, when implemented in a 40-nm CMOS technology. Furthermore, when fabricated in a 180-nm technology, the level-shifting circuit can convert V-DDL as small as 80 mV to 1.8 V without using low-threshold devices.
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[Anonymous], 2006, 2006 S VLSI CIRCUITS, P154, DOI [10.1109/ VLSIC.2006.1705356, DOI 10.1109/VLSIC]